
PIC16(L)F722A/723A
DS41417B-page 176
2010-2012 Microchip Technology Inc.
TABLE 17-7:
SUMMARY OF REGISTERS ASSOCIATED WITH I2C OPERATION
REGISTER 17-5:
SSPMSK: SSP MASK REGISTER
R/W-1
MSK7
MSK6
MSK5
MSK4
MSK3
MSK2
MSK1
MSK0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-1
MSK<7:1>: Mask bits
1 = The received address bit n is compared to SSPADD<n> to detect I2C address match
0 = The received address bit n is not used to detect I2C address match
bit 0
MSK<0>: Mask bit for I2C Slave Mode, 10-bit Address
I2C Slave Mode, 10-bit Address (SSPM<3:0> = 0111):
1 = The received address bit ‘0’ is compared to SSPADD<0> to detect I2C address match
0 = The received address bit ‘0’ is not used to detect I2C address match
All other SSP modes: this bit has no effect.
REGISTER 17-6:
SSPADD: SSP I2C ADDRESS REGISTER
R/W-0
ADD7
ADD6
ADD5
ADD4
ADD3
ADD2
ADD1
ADD0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-0
ADD<7:0>: Address bits
Received address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register on
Page
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
SSPBUF
Synchronous Serial Port Receive Buffer/Transmit Register
SSPADD
Synchronous Serial Port (I2C mode) Address Register
SSPCON
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
SSPMSK(2) Synchronous Serial Port (I2C mode) Address Mask Register
SSPSTAT
SMP(1)
CKE(1)
D/A
PS
R/W
UA
BF
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by SSP
module in I2C mode.
Note 1: Maintain these bits clear in I2C mode.
2: Accessible only when SSPM<3:0> = 1001.